An Architecture for Selective Fault Tolerance and Multiprocessing Using Field-Programmable Hardware

A design approach for selectivity among several traditional hardware fault tolerance methods is proposed. By basing these methods on eld-programmable gate array (FPGA) technology, resources are eeciently used. Each fault tolerance method can be applied to any subset of the redundant modules without the use of steering logic such that the structure of the method is preserved. An architecture supporting this approach is described. An example is given that shows how the architecture supports multiprocessing among the modules.